Printed circuit boards (PCBs) are used extensively in the electronics arts to mount and interconnect discrete electronic components (integrated circuit chips, etc.) to implement a specific function. Commonly, the board substrate is made of polymers and ceramics, although other materials, such as silicon or other semiconductors can be used. It is often desirable to electrically isolate certain components mounted on the PCB from each other and from the board substrate. Typically, this is accomplished by applying one or more layers of dielectric material to the surface of the board and then mounting the components on or in the dielectric layers. For high frequency electronic applications, thick dielectric layers over conductive substrates are needed for form transmission lines.
Common techniques for forming dielectric layers on a wafer of silicon include chemical vapor deposition (CVD) and spin-on-glass (SOG) techniques. These processes are essentially limited to producing dielectric layers of only several microns in thickness, due to inability to effectively prevent cracking in layers of greater thickness and/or their prohibitively slow formation rates. Because of the limitations of thickness of the dielectric layers produced by the above techniques, capacitive coupling problems are not reduced to acceptable levels. That is, capacitive isolation between the substrate and components is not reduced to an acceptable level. The limited thickness of the dielectric layer prevents its use for transmission line applications. Additionally, many of these processes are incapable of forming a dielectric layer having a sufficiently high dielectric constant (e.g., at least 4.1 at 2 degrees C. and 1 MHz) and sufficiently low loss tangent (e.g., at most 0.06 percent at 20 degrees C. and 1 MHz) to permit use of the resulting board in high performance electronics applications (e.g. microwave and/or other radio frequency circuit applications (e.g. microwave and/or other radio frequency circuit applications).
Other techniques used conventionally in the fabrication of glass-on-silicon makes use of the bonding of a glass wafer to a silicon wafer. This process has certain advantages, for example the ability to maintain an acceptably thick layer of glass for transmission lines, as well as an acceptably thick layer of glass/silicon during processing to prevent cracking and thus improve yield. Unfortunately, these techniques require a circumferential lip to effectively bond the glass to the silicon. This technique renders, thereby, a portion of the wafer not useful. The techniques discussed herein can be found in U.S. patent application Ser. No. 08/845,726 to Boles, et al. and U.S. Pat. Nos. 5,268,310 and 5,343,070 to Goodrich, et al., the disclosures of which are specifically incorporated herein by reference. Additionally, discontinuities due to pockets or voids in the glass result in unacceptable dielectric properties and result in an unacceptable degradation in the electrical properties of the resultant heterolithic microwave integrated circuit. To this end, at a corner of a silicon pedestal there is a tendency for a void to form between the silicon and the glass. While the technique used to fabricate the HMIC structure the referenced application to Boles, et al., serves to reduce the voids to acceptable levels, the silicon structures forming the pedestals are limited to those formed by wet-etching techniques. To this end, the silicon is monocrystalline and is anisotropically etched to reveal crystalline planes. These planes enable the bonding of glass without significant voids. Vertical pedestals with substantially right angle corners can not be used due to the large air gaps and poor adhesion of the glass thereto. The presence of these air gaps both limits the size of the pedestals and forces a minimum spacing between pedestals. These factors reduce the number of die that can be fabricated on a wafer and reduces the number of chips that can be placed on a given substrate. Furthermore, the cost of the glass wafers are substantially higher than the cost of the silicon wafer and becomes prohibitively more expensive for wafer diameters larger than 100 mm.
Another technique for fabricating relatively thick layers of electronics grade glass on silicon substrates at lower cost is as disclosed in U.S. Pat. No. 5,639,325 to Stevens, et al. The patent to Stevens, et al., discusses the use of a slurry of glass powder which is prepared with a variety of solvents to include volatile organic solvents and/or water. Additionally, the use of hydrogen is discussed at an ambient temperature of 800.degree. C. This reference to Stevens, et al., while having clear advantages when compared to other techniques for forming a glass layer on a silicon substrate and the article thereby produced compared to the prior techniques, there are certain drawbacks which are inherent in the Stevens, et al. technique. To this end, the reference to Stevens, et al., discloses the use of a particle size of the powder which has an average granular size of about 325 mesh. Particle size as well as variations in the size of the particles can be problematic. In many applications thin glass layers are required, on the order of 5.8 mils. For example, as is disclosed on U.S. patent application Ser. No. 08/845,726, to Boles et al. referenced above, it is necessary to backfill 5-8 mils of glass in thickness between silicon pedestals which are on the order of 3-4 mils in height. When particle size variation ranges in the order of 5-100 microns, it is difficult to effect this desired thickness without multiple firings. To this end, islands on the order of 1 mil can form on the relatively thin glass layer on the order of 0.5 microns which is formed in the first firing. The process must then be repeated to continually increase the thickness and make more uniform the regions between the islands. The reason that the islands are formed is due surface energy effects which occur when the powder starts to melt and due to the variation in size starts to melt into clumps. Accordingly, it is desirable to have a process to fabricate the relatively thick glass layer on the order of 4-12 mils in a variety of applications in a single firing. Another significant drawback to the technique disclosed in the Stevens, et al. patent, is the fact the hydrogen bubbles of a relatively large size remain in the glass as well, creating "pock" marks or craters. The technique disclosed in the reference to Stevens, et al., has clear advantages over prior techniques of forming glass, particularly in a slurry as the hydrogen bubbles are significantly reduced compared to the air bubbles that form and no firing under partial pressure of hydrogen is effected. However, these craters and bubbles have clear disadvantages in uniformity. The hydrogen bubbles can reduce the electronic performance because the glass is not as uniform of a dielectric as is required in electronics grade, particularly high frequency where capacitive coupling is a issue which must be attended to very carefully. Often, the thickness of the glass is reduced to an undesirable level in order to properly grind and polish the surface.
Accordingly, what is needed is a technique for fabricating structures for use in rf and microwave applications having a silicon substrate and a relatively thick and uniform glass layer, that do not suffer from the above described disadvantages of the techniques described above.